A typical computer may have, for example, 32 or 64 megabytes (MB) of random access memory (RAM) that is available for use by the central processing unit (CPU). When a computer is powered on, the CPU loads the operating system (OS) into RAM. Further, when a user runs an application or multiple applications, the CPU loads the applications into RAM. Thus, 32 or 64 MB of RAM may not be enough to run the OS and all of the programs that users may desire to run at a given time.
Typically, virtual memory is used by the OS in order to address the issue that the RAM is not sufficiently large enough to run the OS and various applications simultaneously. Virtual memory is a technique used by the OS that allows the computer to “see” more main memory (e.g., RAM) than it actually has. It does this by using portions of the hard disk to simulate the RAM. In this regard, the accessible memory appears to be a contiguous memory section, while in reality the accessible memory may be physically fragmented and overflow to the hard disk. Such virtual memory is addressable by virtual memory addresses that are mapped to the physical memory addresses of that portion in memory where the content is stored.
Accordingly, during operation there exists a need to translate a virtual memory address requested by an application into a physical memory address. This is often done by a page table, which is a table stored in RAM that comprises virtual address keys corresponding to a plurality of physical addresses.
In addition, most CPUs employ a translation lookaside buffer (TLB), which is a type of cache memory that maps virtual addresses to physical addresses. For a “hardware walked” TLB, during operation a memory management unit (MMU) may use the page table or the TLB to translate a virtual address to a physical address. In a “software walked” TLB, the MMU only uses the entries in the TLB to translate a virtual address to a physical address. Using the TLB to perform such translation tends to speed up the process of virtual-to-physical address translation because the TLB is typically on-processor cache.
As indicated, the TLB is a table that maps virtual addresses to physical addresses. In this regard, software running on the CPU may present a virtual address to the MMU. The MMU searches the TLB for the virtual address and locates the virtual address in the TLB table. The MMU then retrieves the physical address mapped to the virtual address, if the virtual address search is located in the TLB. When the virtual address is found in the TLB, this is referred to as a “TLB hit.” If the virtual address is not found in the TLB, this is referred to as a “TLB miss.”
If a TLB miss occurs, in a “hardware walked” implementation, the MMU then looks up the virtual address in the page table. This is often referred to as a “page walk,” and such process tends to require more time to accomplish because the page table is stored in main memory as opposed to cache like the TLB table.
In a “software walked” implementation, if there is no entry in the TLB that matches the virtual address, a TLB miss exception is raised by the MMU with the CPU. The CPU core executes TLB miss exception handler code that is resident on the CPU to find the correct entry in the page table that is then placed into the TLB to handle the virtual address that is being translated.
Upon returning from the TLB miss exception handler code for a “software walked” implementation or from the page table lookup for a “hardware walked” implementation, the correct virtual-to-physical mapping is inserted as an entry into the TLB for the present access and any future access by the CPU. Such entry into the TLB may specify a cache coherency scheme, a valid bit, and a global bit. The global bit indicates whether the entry into the TLB is static, i.e., cannot be removed, or is dynamic, can be replaced in response to a TLB miss.
The MMU then retries the translation of the virtual to a physical address using the entries in the TLB. In this regard, because the TLB has been updated with a new TLB entry, the translation for the virtual address presented will not fail and access to physical memory will be complete.